Specifies the logical layer for a set of signal lines that constitute a multiple segment bus architecture, and for the interfacing of modules connected to a bus segment. Intended to be used as a component within a profile to build systems with higher levels of compatibility.
Status: WithdrawnPublication date: 1994-12
Edition: 1Number of pages: 208
Technical Committee: ISO/IEC JTC 1 Information technology
- ICS :
- 35.160 Microprocessor systems
ISO/IEC 10857:1994Stage: 95.99
Got a question?
Check out our FAQs
+41 22 749 08 88
Monday to Friday - 09:00-12:00, 14:00-17:00 (UTC+1)
Keep up to date with ISO
Sign up to our newsletter for the latest news, views and product information.